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Semiconductor MSC23V47257TD-XXBS18
DESCRIPTION
This version: Apr. 22. 1999 Previous version: Apr. 1. 1999
4,194,304-Word x 72-Bit DYNAMIC RAM MODULE : FAST PAGE MODE TYPE WITH EDO
The MSC23V47257TD-XXBS18 is a 4,194,304-word x 72-bit CMOS dynamic random access memory module which is composed of eighteen 16Mb(4Mx4) DRAMs in TSOP packages mounted with eighteen decoupling capacitors. This is an 168-pin dual in-line memory module. This module supports any application where high density and large capacity of storage memory are required.
FEATURES
* 4,194,304-word x 72-bit organization * 168-pin Dual In-line Memory Module * Gold tab * Single 3.3V power supply, 0.3V tolerance * Input : LVTTL compatible * Output : LVTTL compatible, 3-state * Refresh : 2048cycles/ 32ms * /CAS before /RAS refresh, hidden refresh, /RAS only refresh capability * Fast page mode with EDO, read modify write capability * Multi-bit test mode capability * Serial Presence Detect
PRODUCT FAMILY
Access Time (Max.) tRAC MSC23V47257TD-50BS18 MSC23V47257TD-60BS18 MSC23V47257TD-70BS18 50ns 60ns 70ns tAA 25ns 30ns 35ns tCAC 13ns 15ns 20ns tOEA 13ns 15ns 20ns Cycle Time (Min.) 84ns 104ns 124ns Power Dissipation (Max.) Operating 6480mW 5832mW 5184mW 32.4mW Standby
Family
Semiconductor
MSC23V47257TD
MODULE OUTLINE
MSC23V47257TD-XXBS18
(Unit : mm) 133.350.7 *1 131.35 TYP 2 - R2.0 25.400.12 17.780.1 3.00.1 4.00Max.
2 - 3.00.1 A 1 11.430.05 36.830.05 127.350.1 133.350.12 54.610.05 B C 84 4.0Min.
1.270.1
R1.0 4.1750.13 3.1750.13
R1.0 1.00.03 0.25 MAX 1.270.03 Detail C
3.120.1
3.120.1
2.00.1 6.350.05 Detail A
2.00.1 6.350.05 Detail B
Note: 1. Tolerance over 19.78mm from bottom edge is 0.7.
2.54 MIN
Semiconductor
MSC23V47257TD
PIN CONFIGURATION
Front Side Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 Pin Name VSS DQ0 DQ1 DQ2 DQ3 VCC DQ4 DQ5 DQ6 DQ7 DQ8 VSS DQ9 DQ10 DQ11 DQ12 DQ13 VCC DQ14 DQ15 CB0 CB1 VSS NC NC VCC /WE0 /CAS0 /CAS1 /RAS0 /OE0 VSS A0 A2 A4 A6 A8 A10 NC VCC VCC NC Back Side Pin No. 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 Pin Name VSS DQ32 DQ33 DQ34 DQ35 VCC DQ36 DQ37 DQ38 DQ39 DQ40 VSS DQ41 DQ42 DQ43 DQ44 DQ45 VCC DQ46 DQ47 CB4 CB5 VSS NC NC VCC NC /CAS4 /CAS5 NC NC VSS A1 A3 A5 A7 A9 NC NC VCC NC NC Front Side Pin No. 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 Pin Name VSS /OE2 /RAS2 /CAS2 /CAS3 /WE2 VCC NC NC CB2 CB3 VSS DQ16 DQ17 DQ18 DQ19 VCC DQ20 NC NC NC VSS DQ21 DQ22 DQ23 VSS DQ24 DQ25 DQ26 DQ27 VCC DQ28 DQ29 DQ30 DQ31 VSS NC NC NC SDA SCL VCC Back Side Pin No. 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 Pin Name VSS NC NC /CAS6 /CAS7 NC VCC NC NC CB6 CB7 VSS DQ48 DQ49 DQ50 DQ51 VCC DQ52 NC NC NC VSS DQ53 DQ54 DQ55 VSS DQ56 DQ57 DQ58 DQ59 VCC DQ60 DQ61 DQ62 DQ63 VSS NC NC SA0 SA1 SA2 VCC
Semiconductor
MSC23V47257TD
Serial PD Matrix SPD Value (Hex) 80 08 02 0B 0B 01 48 00 01 32 /RAS Access Time 3C 46 0D /CAS Access Time 0F 14 DIMM Configuration type Refresh Rate/Type Primary DRAM Width Error Checking DRAM Width Superset Information SPD Data Revision Code -50 63 -60 -70 64-127 128-255 Reserved Unused Storage Location (Reserved) Checksum for Byte 0-62 02 00 04 04 00 01 34 40 4F 00 FF 128 Bytes 256 Bytes EDO 11 11 1 72 0 LVTTL 50ns 60ns 70ns 13ns 15ns 20ns ECC Normal Refresh x4 x4 Reserved 1
Byte No. 0 1 2 3 4 5 6 7 8 -50 9 -60 -70 -50 10 -60 -70 11 12 13 14 15-61 62
Function described Number of Byte used Total SPD Memory size Memory type Number of Rows Number of Columns Number of Banks Module Data Width Module Data Width Continued Supply Voltage
Note
Semiconductor
MSC23V47257TD
BLOCK DIAGRAM
/OE0 /WE0 /RAS0 /CAS0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 /CAS1 DQ8 DQ9 DQ10 DQ11 /CAS /RAS /WE /OE DQ DQ D2 DQ DQ /CAS /RAS /WE /OE DQ DQ D3 DQ DQ /CAS /RAS /WE /OE DQ DQ D4 DQ DQ /CAS /RAS /WE /OE DQ DQ D5 DQ DQ /CAS /RAS /WE /OE DQ DQ D6 DQ DQ /CAS /RAS /WE /OE DQ DQ D0 DQ DQ /CAS /RAS /WE /OE DQ DQ D1 DQ DQ
/OE2 /WE2 /RAS2 /CAS4 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 /CAS5 DQ40 DQ41 DQ42 DQ43 /CAS /RAS /WE /OE DQ DQ D11 DQ DQ /CAS /RAS /WE /OE DQ DQ D12 DQ DQ /CAS /RAS /WE /OE DQ DQ D13 DQ DQ /CAS /RAS /WE /OE DQ DQ D14 DQ DQ /CAS /RAS /WE /OE DQ DQ D15 DQ DQ /CAS /RAS /WE /OE DQ DQ D9 DQ DQ /CAS /RAS /WE /OE DQ DQ D10 DQ DQ
DQ12 DQ13 DQ14 DQ15
DQ44 DQ45 DQ46 DQ47
CB0 CB1 CB2 CB3 /CAS2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 /CAS3 DQ24 DQ25 DQ26 DQ27
CB4 CB5 CB6 CB7 /CAS6 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 /CAS7
/CAS /RAS /WE /OE DQ DQ D7 DQ DQ /CAS /RAS /WE /OE DQ DQ D8 DQ DQ
DQ56 DQ57 DQ58 DQ59
/CAS /RAS /WE /OE DQ DQ D16 DQ DQ /CAS /RAS /WE /OE DQ DQ D17 DQ DQ
DQ28 DQ29 DQ30 DQ31
DQ60 DQ61 DQ62 DQ63
A0-A10 VCC VSS C1-C18
A0-A10 : D0-D17 SCL D0-D17 D0-D17
Serial PD SCL SDA A0 A1 A2 SA0 SA1 SA2
SDA
Semiconductor
MSC23V47257TD
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings Parameter Voltage on Any Pin Relative to VSS Voltage on VCC Supply Relative to VSS Short Circuit Output Current Power Dissipation Operating Temperature Storage Temperature * Ta = 25C Symbol VIN, VOUT VCC IOS PD * TOPR TSTG Rating -0.5 to 4.6 -0.5 to 4.6 50 18 0 to 70 -40 to 125 Unit V V mA W C C
Recommended Operating Conditions ( Ta = 0C to 70C ) Parameter Power Supply Voltage Input High Voltage Input Low Voltage Symbol VCC VSS VIH VIL Min. 3.0 0 2.0 -0.3 Typ. 3.3 0 Max. 3.6 0 VCC+0.3 0.8 Unit V V V V
Capacitance ( VCC = 3.3V 0.3V, Ta = 25C, f = 1 MHz ) Parameter Input Capacitance (A0 - A10) Input Capacitance (/RAS0, /RAS2, /WE0, /WE2, /OE0, /OE2) Input Capacitance (/CAS0 - /CAS7) I/O Capacitance (DQ0 - DQ63, CB0 - CB7) Symbol CIN1 CIN2 CIN3 CI/O Typ. Max. 122 73 28 16 Unit pF pF pF pF
Semiconductor
MSC23V47257TD
DC Characteristics (VCC = 3.3V 0.3V, Ta = 0C to 70C ) Parameter Output High Voltage Output Low Voltage Input Leakage Current Symbol VOH VOL ILI Condition IOH = -2.0mA IOL = 2.0mA 0V VIN VCC+0.3V; All other pins not under test = 0V DQ disable 0V VOUT VCC /RAS, /CAS cycling, tRC = Min. /RAS, /CAS = VIH Power Supply Current (Standby) Average Power Supply Current (/RAS only refresh) Average Power Supply Current (/CAS before /RAS refresh) Average Power Supply Current (Fast Page Mode) ICC2 /RAS, /CAS VCC -0.2V /RAS cycling, /CAS = VIH, tRC = Min. /RAS cycling, /CAS before /RAS /RAS = VIL, /CAS cycling, tHPC = Min. -50 Min. 2.4 0 -180 Max. VCC 0.4 180 Min. 2.4 0 -180 -60 Max. VCC 0.4 180 Min. 2.4 0 -180 -70 Max. VCC 0.4 180 Unit V V A A Note
Output Leakage Current Average Power Supply Current (Operating)
ILO
-10
10
-10
10
-10
10
ICC1
-
1800 36 9
-
1620 36 9
-
1440 36 9
mA mA mA
1, 2
1
ICC3
-
1800
-
1620
-
1440
mA
1, 2
ICC6
-
1800
-
1620
-
1440
mA
1, 2
ICC7
-
1800
-
1620
-
1440
mA
1, 3
Notes: 1. ICC Max. is specified as ICC for output open condition. 2. The address can be changed once or less while /RAS = VIL. 3. The address can be changed once or less while /CAS = VIH.
Semiconductor
MSC23V47257TD
AC Characteristics (1/2) (VCC = 3.3V 0.3V, Ta = 0C to 70C ) Note: 1, 2, 3, 12, 13 Parameter Random Read or Write Cycle Time Read Modify Write Cycle Time Fast Page Mode Cycle Time Fast Page Mode Read Modify Write Cycle Time Access Time from /RAS Access Time from /CAS Access Time from Column Address Access Time from /CAS Precharge Access Time from /OE Output Low Impedance Time from /CAS Data Output Hold After /CAS Low /CAS to Data Output Buffer Turn-off Delay Time /RAS to Data Output Buffer Turn-off Delay Time /OE to Data Output Buffer Turn-off Delay Time /WE to Data Output Buffer Turn-off Delay Time Transition Time Refresh Period /RAS Precharge Time /RAS Pulse Width /RAS Pulse Width (Fast Page Mode with EDO) /RAS Hold Time /RAS Hold Time referenced to /OE /CAS Precharge Time (Fast Page Mode with EDO) /CAS Pulse Width /CAS Hold Time /CAS to /RAS Precharge Time /RAS Hold Time from /CAS Precharge /OE Hold Time from /CAS (DQ Disable) /RAS to /CAS Delay Time /RAS to Column Address Delay Time Row Address Set-up Time Row Address Hold Time Column Address Set-up Time Column Address Hold Time Column Address to /RAS Lead Time Symbol tRC tRWC tHPC tHPRWC tRAC tCAC tAA tCPA tOEA tCLZ tDOH tCEZ tREZ tOEZ tWEZ tT tREF tRP tRAS tRASP tRSH tROH tCP tCAS tCSH tCRP tRHCP tCHO tRCD tRAD tASR tRAH tASC tCAH tRAL -50 Min. 84 110 20 58 0 5 0 0 0 0 1 30 50 50 7 7 7 7 35 5 30 5 11 9 0 7 0 7 25 Max. 50 13 25 30 13 13 13 13 13 50 32 10K 100K 10K 37 25 Min. 104 135 25 68 0 5 0 0 0 0 1 40 60 60 10 10 10 10 40 5 35 5 14 12 0 10 0 10 30 -60 Max. 60 15 30 35 15 15 15 15 15 50 32 10K 100K 10K 45 30 Min. 124 160 30 78 0 5 0 0 0 0 1 50 70 70 13 13 10 13 45 5 40 5 14 12 0 10 0 13 35 -70 Max. 70 20 35 40 20 20 20 20 20 50 32 10K 100K 10K 50 35 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 5 6 7, 8 7, 8 7 7 3 4, 5, 6 4, 5 4, 6 4 4 4 Note
Semiconductor
MSC23V47257TD
AC Characteristics (2/2) (VCC = 3.3V 0.3V, Ta = 0C to 70C ) Note: 1, 2, 3, 12, 13 Parameter Read Command Set-up Time Read Command Hold Time Read Command Hold Time referenced to /RAS Write Command Set-up Time Write Command Hold Time Write Command Pulse Width /WE Pulse Width (DQ Disable) /OE Command Hold Time /OE Precharge Time /OE Command Hold Time Write Command to /RAS Lead Time Write Command to /CAS Lead Time Data-in Set-up Time Data-in Hold Time /OE to Data-in Delay Time /CAS to /WE Delay Time Column Address to /WE Delay Time /RAS to /WE Delay Time /CAS Precharge /WE Delay Time /CAS Active Delay Time from /RAS Precharge /RAS to /CAS Set-up Time (/CAS before /RAS) /RAS to /CAS Hold Time (/CAS before /RAS) /WE to /RAS Precharge Time (/CAS before /RAS) /WE Hold Time from /RAS (/CAS before /RAS) /RAS to /WE Set-up Time (Test Mode) /RAS to /WE Hold Time (Test Mode) Symbol tRCS tRCH tRRH tWCS tWCH tWP tWPE tOEH tOEP tOCH tRWL tCWL tDS tDH tOED tCWD tAWD tRWD tCPWD tRPC tCSR tCHR tWRP tWRH tWTS tWTH -50 Min. 0 0 0 0 7 7 7 7 7 7 7 7 0 7 13 30 42 67 47 5 5 10 10 10 10 10 Max. Min. 0 0 0 0 10 10 10 10 10 10 10 10 0 10 15 34 49 79 54 5 5 10 10 10 10 10 -60 Max. Min. 0 0 0 0 13 10 10 13 10 10 13 13 0 13 20 44 59 94 64 5 5 10 10 10 10 10 -70 Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 10 10 10 10 11 11 9 9 10 Note
Semiconductor
MSC23V47257TD
Notes: 1. A start-up delay of 200s is required after power-up, followed by a minimum of eight initialization cycles (/RAS only refresh or /CAS before /RAS refresh) before proper device operation is achieved. 2. The AC characteristics assume tT = 2ns. 3. VIH(Min.) and VIL(Max.) are reference levels for measuring input timing signals. Transition times (tT) are measured between VIH and VIL. 4. This parameter is measured with a load circuit equivalent to 1 TTL load and 100pF. The output timing reference levels are VOH = 2.0V and VOL = 0.8V. 5. Operation within the tRCD(Max.) limit ensures that tRAC(Max.) can be met. tRCD(Max.) is specified as a reference point only. If tRCD is greater than the specified tRCD(Max.) limit, then the access time is controlled by tCAC. 6. Operation within the tRAD(Max.) limit ensures that tRAC(Max.) can be met. tRAD(Max.) is specified as a reference point only. If tRAD is greater than the specified tRAD(Max.) limit, then the access time is controlled by tAA. 7. tCEZ(Max.), tREZ(Max.), tWEZ(Max.) and tOEZ(Max.) define the time at which the output achieves the open circuit condition and are not referenced to output voltage levels. 8. tCEZ or tREZ must be satisfied for open circuit condition. 9. tRCH or tRRH must be satisfied for a read cycle. 10. tWCS, tCWD, tRWD, tAWD and tCPWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCS tWCS(Min.), then the cycle is an early write cycle and the data out will remain open circuit (high impedance) throughout the entire cycle. If tCWD tCWD(Min.), tRWD tRWD(Min.), tAWD tAWD(Min.) and tCPWD tCPWD(Min.), then the cycle is a read modify write cycle and data out will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, then the condition of the data out (at access time) is indeterminate. 11. These parameters are referenced to the /CAS leading edge in an early write cycle, and to the /WE leading edge in an /OE control write cycle, or a read modify write cycle. 12. The test mode is initiated by performing a /WE and /CAS before /RAS refresh cycle. This mode is latched and remains in effect until the exit cycle is generated. The test mode specified in this data sheet is an 8-bit parallel test function. CA0, CA1 and CA10 are not used. In a read cycle, if all internal bits are equal, the DQ pin will indicate a high level. If any internal bits are not equal, the DQ pin will indicate a low levels. The test mode is cleared and the memory device returned to its normal operating state by performing a /RAS only refresh cycle or a /CAS before /RAS refresh cycle. 13. In a test mode read cycle, the value of access time parameters is delayed for 5ns for the specified value. These parameters should be specified in test mode cycle by adding the above value to the specified value in this data sheet.

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